Automatic layout design method of wirings in integrated circuit

Details Automatic layout design method of wirings in integrated circuit Automatic layout design method of wirings in integrated circuit

1995-04-21

1996-12-10

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364491, 364488, 257499, 257923, 257208, 257503, G06F 1500

Patent

active

055837883

ABSTRACT:
A method, according to a hierarchical processing used for a computer-aided design system, for automatically wiring a circuit by dividing a region into a plurality of coarse global grids. The automatic wiring method includes the steps of: setting up and calculating an evaluation function having therein a plurality of evaluation terms for indicating selectability by which the cut-line is preferentially selected so that a wiring congestion is most relaxed; giving weights to the respective plurality of evaluation terms and defining an evaluation function which totals the plurality of the evaluation terms; dividing the region into two by a cut-line having a minimum value in the evaluation functions; determining a position to cross all nets crossing the cut-line; and performing the above steps recursively and hierarchically until the divided regions become a predetermined minimum size.

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