Layout design method of semiconductor integrated circuit

Details Layout design method of semiconductor integrated circuit Layout design method of semiconductor integrated circuit

2009-01-23

2011-10-04

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S050000, C716S052000, C716S103000, C716S104000, C716S112000, C716S132000, C716S136000

Reexamination Certificate

active

08032847

ABSTRACT:
A layout design method of a semiconductor integrated circuit includes degenerating a layout netlist extracted from layout data, comparing the layout netlist after the reduction with a circuit diagram netlist, and creating a layout circuit association table of a layout cell after the reduction and a circuit element. The method includes creating a before and after reduction association table based on the layout netlist before and after the reduction, counting the number of layout elements in a layout cell area before the reduction, comparing the counted number of layout elements and the number of degenerated elements, and creating mapping information associating the layout cell with the circuit element.

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