Memory system having a vertical bitline topology and method ther

Details Memory system having a vertical bitline topology and method ther Memory system having a vertical bitline topology and method ther

1997-10-28

1999-03-02

Nelms, David

Static information storage and retrieval

Interconnection arrangements

36523005, 36518904, 365156, 365190, G11C 506

Patent

active

058779760

ABSTRACT:
An improved topology for multi-port memory cell layouts in which two or more bitline pairs are required for data transfers is provided. Bitlines are displaced vertically, rather than horizontally. Such vertical spacing provides improved silicon density while reducing bitline capacitance of a memory cell. Additionally, the use of vertically separated bitline pairs allows traditional transitional phase relationships between multi-port operations in multi-port memory implementations. To nullify any sensitivity to an overlapping restore operation, this improved topology includes cross-coupled ports.

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