Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2008-03-21
2011-10-18
Pham, Thanh V (Department: 2894)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S647000, C257SE21540
Reexamination Certificate
active
08039358
ABSTRACT:
A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping.
REFERENCES:
patent: 5960299 (1999-09-01), Yew et al.
patent: 2003/0100166 (2003-05-01), Pividori
patent: 2005/0227440 (2005-10-01), Ema et al.
patent: 2006/0040462 (2006-02-01), Wu et al.
patent: 2006/0189092 (2006-08-01), Sato et al.
patent: 2007/0065731 (2007-03-01), Ishiwata
patent: 2001-024055 (2001-01-01), None
patent: 2004-186551 (2004-07-01), None
patent: 1020050002089 (2005-01-01), None
patent: 10-2005-0069519 (2005-07-01), None
Korean Office Action dated Oct. 18, 2010, issued in corresponding Korean Patent Application No. 10-2008-0028928.
Korean Office Action dated Sep. 14, 2010, issued in corresponding Korean Patent Application No. 10-2010-0056228.
Nakagawa Masaki
Terahara Masanori
Fujitsu Semiconductor Limited
Nguyen Duy
Pham Thanh V
Westerman Hattori Daniels & Adrian LLP
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