Three dimensional memory in a system on a chip

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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C716S100000, C716S101000, C716S102000, C716S103000, C716S104000, C716S105000, C716S117000, C716S118000, C716S119000, C716S138000, C365S129000, C365S130000, C365S131000

Reexamination Certificate

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08042082

ABSTRACT:
The invention relates to multi-planar memory components in a three-dimensional integrated circuit system configuration. A multi-planar memory system consisting of a plurality of memory circuit planes in a three-dimensional system on a chip (3D SoC) comprised of a plurality of memory layers, at least one logic circuit layer and an interface configured to provide access to memory and logic circuit layers.

REFERENCES:
patent: 5502667 (1996-03-01), Bertin et al.
patent: 6515888 (2003-02-01), Johnson et al.
patent: 7193239 (2007-03-01), Leedy
patent: 7402897 (2008-07-01), Leedy
patent: 7633789 (2009-12-01), Norman
patent: 7692448 (2010-04-01), Solomon

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