Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2008-08-20
2011-10-11
Pert, Evan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S272000, C257S392000, C257SE21631
Reexamination Certificate
active
08035139
ABSTRACT:
A dynamic random access memory (DRAM) device can include a plurality of memory cells. Each memory cell can include a charge storing structure and an access device comprising an enhancement mode junction field effect transistor (JFET). The DRAM device can further include a plurality of sense amplifiers that each generates an output value in response to a signal received at respective sense amplifier inputs, and a plurality of bit lines, each bit line coupling a plurality of memory cells to at least one input of at least one of the sense amplifiers. A method can fabricate such DRAM devices.
REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 3412286 (1968-11-01), Grebene
patent: 3936929 (1976-02-01), Bean et al.
patent: 3951702 (1976-04-01), Kano et al.
patent: 3967305 (1976-06-01), Zuleeg
patent: 3986180 (1976-10-01), Cade
patent: 4126899 (1978-11-01), Lohstroh et al.
patent: 4126900 (1978-11-01), Koomen et al.
patent: 4228367 (1980-10-01), Brown
patent: 4333224 (1982-06-01), Buchanan
patent: 4638344 (1987-01-01), Cardwell, Jr.
patent: 4751556 (1988-06-01), Cogan et al.
patent: 4777517 (1988-10-01), Onodera et al.
patent: 4791611 (1988-12-01), Eldin et al.
patent: 5130770 (1992-07-01), Blanc et al.
patent: 5140551 (1992-08-01), Chiu
patent: 5243209 (1993-09-01), Ishii
patent: 5393998 (1995-02-01), Ishii et al.
patent: 5589409 (1996-12-01), Bulucea et al.
patent: 5618688 (1997-04-01), Reuss
patent: 5773891 (1998-06-01), Delgado
patent: 5973341 (1999-10-01), Letavic et al.
patent: 2002/0197779 (2002-12-01), Evans
patent: 2007/0096144 (2007-05-01), Kapoor
patent: 2007/0284628 (2007-12-01), Kapoor
patent: 2008/0001183 (2008-01-01), Kapoor
patent: 2008/0237657 (2008-10-01), Kapoor
patent: 2008/0273398 (2008-11-01), Vora
patent: 0 050 772 (1982-05-01), None
patent: 2208967 (1989-04-01), None
patent: 60258948 (1985-12-01), None
patent: 08-78435 (1996-03-01), None
PCT International Search Report for International Application No. PCT/US2008/074706, dated Mar. 30, 2009.
PCT Written Opinion of the International Searching Authority for International Application No. PCT/US2009/074706, dated Mar. 30, 2009.
Heald et al., Multilevel Random-Access Memory Using One Transistor Per Cell, IEEE Journal of Solid-State Circuits, Aug. 1976, vol. SC-11, No. 4, pp. 519-528.
Shin et al., A High-Speed Low-Power JFET Pull-Down ECL Circuit, IEEE Journal of Solid-State Circuits, Apr. 1991, vol. 26, No. 4, pp. 679-682.
Horowitz et al., “Non-Volatile and Fast Static Memories”, ISSCC 90, Feb. 14, 1990, pp. 68-69, 267.
Haverstock & Owens LLP
Pert Evan
SuVolta, Inc.
Wilson Scott R
LandOfFree
Dynamic random access memory having junction field effect... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic random access memory having junction field effect..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic random access memory having junction field effect... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4286177