Semiconductor memory device capable of detecting write...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S189050, C365S189160, C365S207000, C365S236000

Reexamination Certificate

active

08040735

ABSTRACT:
A memory cell array has a plurality of memory cells arrayed in row and column directions. A plurality of sense amplifier units includes a plurality of sense amplifiers detecting write completion of each of the memory cells selected for each row. A plurality of detection units is arranged correspondingly to the sense amplifier units, and forms a transfer path for transferring potential in accordance with a detection output signal of each sense amplifier unit. The detection units detect a sense amplifier unit corresponding to a portion where the transfer path breaks off, as a sense amplifier unit including write incompletion bit.

REFERENCES:
patent: 5566113 (1996-10-01), Saito et al.
patent: 2006/0291291 (2006-12-01), Hosono et al.
patent: 2006-277786 (2006-10-01), None
patent: 2007-102942 (2007-04-01), None

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