Wiring structure, semiconductor device and manufacturing...

Details Wiring structure, semiconductor device and manufacturing... Wiring structure, semiconductor device and manufacturing...

2006-09-15

2011-10-18

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

C257S522000

Reexamination Certificate

active

08039921

ABSTRACT:
A semiconductor device with a high-strength porous modified layer having a pore size of 1 nm or less, which is formed, in a multilayer wiring forming process, by forming a via hole and a wiring trench in a via interlayer insulating film and a wiring interlayer insulting film and then irradiating an electron beam or an ultraviolet ray onto the opening side walls.

REFERENCES:
patent: 6670709 (2003-12-01), Usami
patent: 7030468 (2006-04-01), Gates et al.
patent: 7270849 (2007-09-01), Hayashi
patent: 7282458 (2007-10-01), Gates et al.
patent: 2001/0017402 (2001-08-01), Usami
patent: 2004/0029386 (2004-02-01), Lee et al.
patent: 2005/0156285 (2005-07-01), Gates et al.
patent: 2005/0267253 (2005-12-01), Hayashi
patent: 2006/0055004 (2006-03-01), Gates et al.
patent: 2007/0108593 (2007-05-01), Ogihara et al.
patent: 2007/0157884 (2007-07-01), Hayashi
patent: 2000-183052 (2000-06-01), None
patent: 2001-85522 (2001-03-01), None
patent: 2001-223269 (2001-08-01), None
patent: 2004-47873 (2004-02-01), None
patent: 2004-96080 (2004-03-01), None
patent: 2004-193326 (2004-07-01), None
patent: 2004-221104 (2004-08-01), None
patent: 2004-274052 (2004-09-01), None
patent: 2005-51192 (2005-02-01), None
patent: 2005-79307 (2005-03-01), None
patent: 2005-142433 (2005-06-01), None
patent: 2005-203794 (2005-07-01), None
Hayashi Y. et al., “Novel molecular-structure design for PECVD porous SiOCH films toward 45nm node, ASICs with k=2.3.” In: Proceedings of the IEEE 2004 International Interconnect Technology Conference, 2004, p. 225-227 p. 1178-1184.
Yoshihiro Hayashi, “Tei Yudenritsu Zetsuenmaku Zairyo no Shinka to Saisentan ULSI Taso Haisen Gijutsu”, Oyo Butsuri, Sep. 10, 2005, vol. 74, No. 9, pp. 1178 to 1184.

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