Semiconductor chip mounting body, method of manufacturing...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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Details

C257S783000, C257SE23010, C257SE23116

Reexamination Certificate

active

08035212

ABSTRACT:
According to one embodiment, a semiconductor chip mounting body, with an enhanced shock-resistance at portions of the bonding member corresponding to the corners of a semiconductor chip, is provided. The semiconductor chip mounting body includes a circuit board having a circuit pattern formed on a mounting surface thereof, a semiconductor chip mounted on the circuit pattern of the circuit board, and a bonding member arranged at least between the circuit board and the semiconductor chip, and on the sides of the semiconductor chip to fix the semiconductor chip on the circuit board. The bonding member contains thermosetting resin and magnetic powder dispersed in the thermosetting resin. The magnetic powder is locally disposed in portions of the bonding member which is located the corners of the semiconductor chip.

REFERENCES:
patent: 2007/0068622 (2007-03-01), Konishi
patent: 2009/0179537 (2009-07-01), Morino et al.
patent: 62-22383 (1987-01-01), None
patent: 06-061302 (1994-03-01), None
patent: 08-088248 (1996-04-01), None
patent: 2000-077476 (2000-03-01), None
patent: 2000-294601 (2000-10-01), None
patent: 2002-57191 (2002-02-01), None
patent: 2004-185857 (2004-07-01), None
patent: 2004-288946 (2004-10-01), None
patent: 2005-303335 (2005-10-01), None
patent: 2008-060403 (2008-03-01), None
patent: 2008-060525 (2008-03-01), None
Notice of Reason for Rejection mailed by Japan Patent Office on Feb. 16, 2010 in the corresponding Japanese patent application No. 2009-098267.
Final Notice of Reason for Rejection mailed by Japan Patent Office on May 25, 2010 in the corresponding Japanese patent application No. 2009-098267.
Explanation of Non-English Language References.

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