High-speed memory package

Details High-speed memory package High-speed memory package

2008-02-20

2011-11-22

Lebentritt, Michael (Department: 2829)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S713000, C257S720000, C257S723000, C257SE23039, C257SE23083

Reexamination Certificate

active

08063481

ABSTRACT:
The semiconductor package includes a dielectric layer, a trace layer, a conductive layer, a die and an underfill layer. The dielectric layer has first side and an opposing dielectric layer second side. Multiple vias extend through the dielectric layer from the dielectric layer first side to the dielectric layer second side. Multiple solder balls are disposed at the dielectric layer second side. Each of the solder balls is electrically coupled to a different one of the vias. The die is electrically coupled to the solder balls. The conductive layer is disposed between the dielectric layer second side and the die. The conductive layer defines a window there through for allowing the solder balls to electrically couple to the vias without contacting the conductive layer, i.e., no physical or electrical contact. The underfill layer is formed between the die and the conductive layer, while the trace layer is formed at the dielectric layer first side. Traces of the trace layer electrically couple the vias to other solder balls.

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International Search Report and Written Opinion issued in PCT/US2008/054455, Jun. 24, 2008, 9 pages by ISA/EP.

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