Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2009-07-24
2011-10-11
Potter, Roy K (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S112000
Reexamination Certificate
active
08034660
ABSTRACT:
An electronic assembly adapted for forming package on package (PoP) devices includes a package substrate having a molded IC die thereon that defines a mold cap height and substrate contact pads lateral to the molded IC die. An interposer including an interposer substrate has bottom metal land pads and top metal land pads, interposer vias, and an open receptacle region formed through the interposer substrate. The substrate top surface is positioned relative to the interposer so that the molded IC die is within the open receptacle region to align the bottom metal land pads and substrate contact pads. An underfill layer is between the substrate top surface and the bottom side of the interposer substrate. A step height from the mold cap height minus a height of the top metal land pads is generally from 0 to 0.2 mm.
REFERENCES:
patent: 7198980 (2007-04-01), Jiang et al.
patent: 2009/0121346 (2009-05-01), Wachtler
Brady III Wade J.
Potter Roy K
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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