Non-volatile memory device having configurable page size

Details Non-volatile memory device having configurable page size Non-volatile memory device having configurable page size

Filed on

2008-12-08

Date issued

2011-11-29

Examiner

Auduong, Gene N. (Department: 2827)

Patent Class

Static information storage and retrieval

SubClass

Floating gate

SubSubClass

Particular connection

Other Related Categories

C365S185230

Type

Reexamination Certificate

Status

active

Patent number

08068365

Description

ABSTRACT:
A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.

REFERENCES:
patent: 5369619 (1994-11-01), Ohba
patent: 5752275 (1998-05-01), Hammond
patent: 6041016 (2000-03-01), Freker
patent: 6240040 (2001-05-01), Akaogi et al.
patent: 6516399 (2003-02-01), Anand
patent: 6523102 (2003-02-01), Dye et al.
patent: 6763424 (2004-07-01), Conley
patent: 6850438 (2005-02-01), Lee et al.
patent: 6889304 (2005-05-01), Perego et al.
patent: 6889307 (2005-05-01), Scheuerlein
patent: 7096313 (2006-08-01), Chang et al.
patent: 7154783 (2006-12-01), Lee et al.
patent: 7197607 (2007-03-01), Roohparvar
patent: 7254075 (2007-08-01), Woo et al.
patent: 7389402 (2008-06-01), Zuraski, Jr. et al.
patent: 7505356 (2009-03-01), Ware et al.
patent: 7755968 (2010-07-01), Woo et al.
patent: 7779214 (2010-08-01), Stecher
patent: 7889544 (2011-02-01), Chow et al.
patent: 7953931 (2011-05-01), Yu et al.
patent: 2004/0027856 (2004-02-01), Lee
patent: 2006/0067146 (2006-03-01), Woo et al.
patent: 2007/0076484 (2007-04-01), Cho et al.
patent: 2007/0242552 (2007-10-01), Ju
patent: 2007/0263457 (2007-11-01), Park
Lee June. et al., “A 90-nm CMOS 1.8-V 2-Gb NAND Flash Memory for Mass Storage Applications” 1934 IEEE Journal of Solid-State Circuits, vol. 38, No. 11 1493 0018-9200/03 © 2003, Nov. 2003, pp. 1934-1942.
Samsung Electronics “512M × 8 Bit / 1G × 8 Bit NAND Flash Memory” Flash Memory K9F4G08U0A, K9K8G08U1A, K9XXG08UXA. Mar. 7, 2006. pp. 1-43.
Samsung Electronics “1G × 8 Bit/ 2G × 8 Bit NAND Flash Memory” Flash Memory K9KAG08U1M, K9F8G08U0M, K9F8G08B0M and K9F8G08UXM. Mar. 31, 2007. pp. 1-54.
Samsung Electronics “64M × 8 Bits NAND Flash Memory” Flash Memory K9F1208R0C, K9F1208U0C, K9F1208B0C and K9F1208X0C. Jun. 18, 2007. pp. 1-38.
Lee, Seungjae et al., “A 3.3V 4Gb Four-Level NAND Flash Memory with 90nm CMOS Technology”, ISSCC 2004 / Session 2 / Non-Volatile Memory / 2.72004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/© 2004 IEEE, 2004, pp. 1-10.
Imamiya, Kenichi et al., “A 125-mm2 1-Gb NAND Flash Memory With 10-MByte/s Program Speed”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002 1493 0018-9200/02 © 2002 IEEE. Nov. 2002. pp. 1493-1501.
Suh, Kang-Deog et al., “A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme, ”IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995 1149 0018-9200/95 a 1995 IEEE, Nov. 1995, pp. 1149-1156.
Kim, Jin-Ki et al., “A 120-mm2 64-Mb NAND Flash Memory Achieving 180 ns/Byte Effective Program Speed” 670 IEEE Journal of Solid-State Circuits, vol. 32, No. 5, May 1997 0018-9200/97 a 1997 IEEE. May 1997. pp. 670-680.
Byeon, Dae-Seok et al. “An 8Gb Multi-Level NAND Flash Memory with 63nm STI CMOS Process Technology”. 46 ISSCC 2005 / Session 2 / Non-Volatile Memory /2.2 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/ © 2005 IEEE. 2005. pp. 46-47.
Hara, Takahiko et al. , “A 146mm2 8Gb NAND Flash Memory with 70nm CMOS Technology”, ISSCC 2005 / Session 2 / Non-Volatile Memory / 2.144 • 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/ © 2005 IEEE. 2005. pp. 44-46.
Yoo et al., “A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 GByte/s Bandwidth”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1635-1644.
Gal et al., “Algorithms and Data Structures for Flash Memories”, Tel Aviv University, ACM Computing Surveys, vol. 37, No. 2, Jun. 2005, pp. 138-163.
PCT Application No. PCT/CA2009/000004: International Search Report dated Apr. 9, 2009, p. 2.
PCT Application No. PCT/CA2009/000130: International Search Report, dated May 19, 2009, p. 2.

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