MOS field-effect transistor and manufacturing method thereof

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric

Reexamination Certificate

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C438S739000, C438S214000, C438S282000, C438S411000

Reexamination Certificate

active

08067291

ABSTRACT:
To provide a manufacturing method of a MOS field-effect transistor in which such a structure is adopted that SiGe having a large lattice constant is embedded immediately below a channel and distortion is effectively introduced in a channel Si layer so that mobility of electrons or holes are drastically improved, thereby realizing high-speed operation and low power consumption. A stressor2composed of silicon germanium is formed in a portion in an active region that is separated by an insulating film formed on a silicon substrate, a silicon channel layer1composed of silicon is formed above the stressor, and a tensile stress layer10is formed so as to surround a gate electrode and a sidewall formed on the gate electrode.

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International Search Report of PCT/JP2004/013531, date of mailing Dec. 7, 2004.

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