Semiconductor device including thyristor and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor

Reexamination Certificate

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C257SE21388, C257SE27079, C257SE29211, C257SE29214, C257SE29295, C438S135000

Reexamination Certificate

active

08049248

ABSTRACT:
A semiconductor device includes a thyristor in which a first-conductivity-type first region, a second-conductivity-type second region having a conductivity type reverse to the first conductivity type, a first-conductivity-type third region, and a second-conductivity-type fourth region are sequentially arranged to form junctions. The third region is formed on a semiconductor substrate separated by an element isolation region. A gate electrode formed via a gate insulating film and side wall formed at wall side of both side of the gate electrode are provided on the third region, and the fourth region is formed so that one end thereof covers the joint portion between the other end of the third region and the element isolation regions, and so that the other end of the fourth region is joined with the sidewall on the other side.

REFERENCES:
patent: 6462359 (2002-10-01), Nemati et al.
patent: 6888176 (2005-05-01), Horch et al.
patent: 2007/0138501 (2007-06-01), Sugizaki et al.
Nemati et al., “A novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device”, 1998 IEEE, VLSI Technology tech. Dig. p. 66, 1998.
Nemati et al., “A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed. Low-Voltage, Giga-scale Memories”, 1999 IEEE IEDM Tech., 183, 1999.
Nemati et al., “Fully Planar 0.5621μm2 T-RAM Cell in a 130nm SOI CMOS Logic Technology for High-Density High-Performance SRAMs”, T-RAM Inc., IEEE 2004.

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