Verification support apparatus, verification support method,...

Details Verification support apparatus, verification support method,... Verification support apparatus, verification support method,...

2009-03-17

2011-12-06

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S107000, C716S111000, C703S016000

Reexamination Certificate

active

08074192

ABSTRACT:
The circuit volume of a system under design is reduced by a circuit conversion involving consolidation (sharing) of common parts in the system by a representative part. The design data of the system post-conversion is used to verify operation of the system. However, the verification results for the system post-conversion express signals (e.g., signal X) of plural modules (e.g., modules a to c) as one signal waveform thereby making debugging difficult when a bug is found. Given this situation, from the verification results of the system post-conversion, signal-generation-use data is generated for generating the signal waveforms (here, respective signal waveforms for the modules a to c) of the system before conversion. After verification is complete, a signal waveform for each of the modules a to c is generated using the verification results for the system under design and the signal-generation-use data.

REFERENCES:
patent: 7966590 (2011-06-01), Kanazawa et al.
patent: 2008/0312881 (2008-12-01), Kanazawa et al.
patent: 2000-215226 (2000-08-01), None
patent: 2008-250644 (2008-10-01), None
U.S. Appl. No. 12/076,551, Yuzi Kanazawa et al.

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