Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-12-13
2011-10-18
Lefkowitz, Sumati (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
08040315
ABSTRACT:
A display device includes a scanning line drive circuit, which includes plural stages of D type of flip-flops (DFFs) connected in cascade. The first DFF stage receives a pixel signal of video data to be displayed. These DFF stages have outputs respectively connected to AND gates. The DFF stages and AND gates receive a common clock signal. The DFF stages are responsive to the clock signal to sequentially shift respective values held therein to the following stages with delay. Thus, a drive device is provided which can drive a display panel in a simple configuration without using an OE (Output Enable) signal.
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Japanese Office Action “Notification of Reason for Refusal” with mailing date of Aug. 30, 2011; Japanese Patent Application No. 2005-378254 with extract translation.
Amadiz Rodney
Lefkowitz Sumati
Oki Semiconductor Co., Ltd.
Studebaker Donald R.
Studebaker & Brackett PC
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