Clock and data recovery circuit

Details Clock and data recovery circuit Clock and data recovery circuit

2008-04-08

2011-10-11

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

C375S294000, C375S327000, C375S371000, C375S375000, C375S376000, C327S157000, C331S011000, C331S016000, C331S017000

Reexamination Certificate

active

08036318

ABSTRACT:
The phase detector compares the phases of a synchronous clock signal and serial data and outputs a phase error signal corresponding to a comparison result. The second integrator performs integration of the phase error signal to obtain a phase correction control signal for tracking phase shift of the serial data. The first integrator performs integration of the phase error signal in each smoothing period with a predetermined length to obtain a smoothed error signal. The pattern generator generates a pattern for changing the phase of the synchronous clock signal at a frequency corresponding to the smoothed error signal in each pattern generation period with a predetermined length and outputs the pattern as a frequency correction control signal. The first integrator receives the frequency correction control signal which is fed back and changes the length of the smoothing period according to the direction of a change in the frequency of generating the frequency correction control signal.

REFERENCES:
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patent: 7362185 (2008-04-01), Yildiz et al.
patent: 7737792 (2010-06-01), Kawamoto et al.
patent: 7746971 (2010-06-01), Masui et al.
patent: 2004/0252804 (2004-12-01), Aoyama
patent: 2006/0056564 (2006-03-01), Takeuchi
patent: 2007/0018745 (2007-01-01), Knotts et al.
patent: 2005-5999 (2005-01-01), None

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