Phase locked loop

Details Phase locked loop Phase locked loop

1997-12-03

1999-03-02

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 1A, 331 25, 327156, 327157, 327159, 327 7, H03L 7085, H03L 7089

Patent

active

058776583

ABSTRACT:
A phase locked loop comprises a voltage controlled oscillator, a 1
frequency demultiplier, a phase comparator, and a modulation circuit. The phase comparator is supplied with a first signal which varies according to a reference clock signal and a second signal which varies according to a feedback signal supplied from the 1
frequency demultiplier, executes phase comparison between the two signals, and controls the oscillation frequency of the voltage controlled oscillator by varying a control voltage by outputting an up-control signal or a down-control signal depending on phase difference between the signals. The modulation circuit generates the first signal by periodically modulating the reference clock signal with a shift width which is larger than the dead zone width of the phase comparator, and supplies the phase comparator with the first signal. Preferably, a 1/2 delay circuit is provided between the 1
frequency demultiplier and the phase frequency comparator, for delaying the feedback signal by half the shift width. According to the phase locked loop, perfectly linear characteristic around the stationary state and elimination of stationary phase difference are realized.

REFERENCES:
patent: 4023116 (1977-05-01), Alfke et al.
patent: 5436596 (1995-07-01), Folmer
patent: 5699387 (1997-12-01), Seto et al.
Patent Abstract of Japan, vol. 011, No. 275 (E-537), 5 Sep. & JP No. 62 076324 A (Japan Radio Co Ltd.), 8 Apr. 1987.
Patent Abstract of Japan, vol. 096, No. 012, 26 Dec. 1996 & JP 08 213905 A (Hitachi Ltd), 20 Aug. 1996.

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