Parallel optoelectronic neural network processors

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364807, G06F 1518

Patent

active

050088335

ABSTRACT:
Several embodiments of neural processors implemented on a VLSI circuit chip are disclosed, all of which are capable of entering a matrix T into an array of photosensitive devices which may be charge coupled or charge injection devices (CCD or CID). Using CCD's to receive and store the synapses of the matrix T from a spatial light modulator, or other optical means of projecting an array of pixels, semiparallel synchronous operation is achieved. Using CID's, full parallel synchronous operation is achieved. And using phototransistors to receive the array of pixels, full parallel and asynchronous operation is achieved. In the latter case, the source of the pixel matrix must provide the memory necessary for the matrix T. In the other cases, the source of the pixel matrix may be turned off after the matrix T has been entered and stored by the CCD's or CID's.

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