Semiconductor integrated circuit designing method

Details Semiconductor integrated circuit designing method Semiconductor integrated circuit designing method

2008-06-10

2011-11-22

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

C716S110000, C716S111000, C716S114000, C716S115000, C716S119000

Reexamination Certificate

active

08065639

ABSTRACT:
An IC designing method includes planning placement of a first isolated-power supplied region operating between common ground and power bus lines during a normal operation, and second/third isolated-power supplied regions each operating between the common ground bus line and first/second isolated power lines and supplied with potentials different from the common power supply, planning placement of first electrostatic protection circuits connected between the common ground power bus lines and between the common ground bus line and the first/second isolated power lines, and second electrostatic protection circuits connected between the first/second isolated power lines and the common power bus lines, judging presence of a signal transmission between non-adjacent regions among the first to third isolated-power supplied regions, and amending the circuit to insert a buffer circuit powered by the common power bus line in a transmission path when the signal transmission is present.

REFERENCES:
patent: 6075686 (2000-06-01), Ker
patent: 2005/0152081 (2005-07-01), Worley
patent: 2006/0218518 (2006-09-01), Hirata
patent: 2007/0223163 (2007-09-01), Hung et al.
patent: 2001298157 (2001-10-01), None
Japanese Office Action dated Jun. 30, 2009, corresponding to U.S. Application No. 12/136,230, filed Jun. 10, 2008.

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