Semiconductor device having spaced unit regions and heavily...

Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With non-planar semiconductor surface

Reexamination Certificate

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Details

C257S590000, C257SE29027, C257SE29037, C257SE29197

Reexamination Certificate

active

07745906

ABSTRACT:
An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.

REFERENCES:
patent: 5751024 (1998-05-01), Takahashi
patent: 5869850 (1999-02-01), Endo et al.
patent: 6262470 (2001-07-01), Lee et al.
patent: 7-58320 (1995-03-01), None
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patent: 9-148574 (1997-06-01), None
patent: 2000-286416 (2000-10-01), None
patent: 2000286416 (2000-10-01), None
patent: 1989-0013770 (1989-09-01), None
patent: 1991-0007160 (1991-04-01), None
patent: 1997-0077752 (1997-12-01), None
patent: 1999-015506 (1999-03-01), None
patent: 2000-0064345 (2000-11-01), None
patent: 2002-0071768 (2002-09-01), None
patent: 10-2005-0083340 (2005-08-01), None
patent: 434900 (2001-05-01), None
patent: I256724 (2006-06-01), None
patent: WO 95/24055 (1995-09-01), None

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