Semiconductor chip with stratified underfill

Details Semiconductor chip with stratified underfill Semiconductor chip with stratified underfill

2007-09-04

2010-06-29

Geyer, Scott B (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Encapsulating

C257S787000

Reexamination Certificate

active

07745264

ABSTRACT:
Various semiconductor chip underfills and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate to leave a gap therebetween, and forming an underfill layer in the gap. The underfill layer includes a first plurality of filler particles that have a first average size and a second plurality of filler particles that have a second average size smaller than the first average size such that the first plurality of filler particles is concentrated proximate the substrate and the second plurality of filler particles is concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer is larger proximate the substrate than proximate the semiconductor chip.

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