Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1984-05-07
1986-01-14
Ozaki, George T.
Metal working
Method of mechanical manufacture
Assembling or joining
29577C, 29578, 29580, H01L 21203
Patent
active
045638063
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a method for the manufacture of an active matrix display screen, based on thin-film transistors (TFT) and capacitors).It is used more particulary in the construction of liquid crystal display circuits.
TFT circuits are mainly used in the manufacture of active matrix display screens. In this type of screen, an electronic memory formed from memory points distributed over the entire surface of the screen, stores the video signal throughout the duration of the picture. The electrooptical transducer (e.g. a liquid crystal) is in contact with each memory point and is excited throughout the duration of a picture whereas in system without an electronic memory, the transducer is only excited for the duration of one row. The optical effect and the permitted multiplexing level are consequently much greater.
The TFT makes it possible to produce such an electronic memory on a glass substrate. Each memory point is located at the intersection of a connection column and a row and is constituted by a transistor and a capacitor. In the case where the transducer is a liquid crystal, the plates of the capacitor can be constituted by the electrodes of the actual liquid crystal cell. Thus, the memory point amounts to a TFT and a capacitor, whereof one of the plates is constituted by the electrode arranged on the wall of the cell containing the TFT, the other plate being formed by the counter-electrode arranged on the other wall of the cell.
Such a structure is shown in FIG. 1, where it is possible to see on the one hand a lower wall 10 carrying the conductive columns 12 and conductive rows 14, a TFT 20 and a transparent electrode 22, and on the other hand an upper wall 24 covered by an also transparent counter-electrode 26.
Besides active matrixes, other circuits can be produced with TFT's and, e.g., all or part of shift registers. Such circuits can be used in the low speed vertical register permitting the row-by-row switching of the display screen.
Methods for the manufacture of circuits based on TFT's and capacitors are already known. FIG. 2 (a, b) illustrates a procedure described by A. J. SNELL et al. in an article entitled "Application of amorphous silicon field effect transistors in addressable liquid crystal display panels" published in "Applied Physics", 24, pp. 357-362, 1981. The TFT is formed by a chromium grid G deposited on an insulating substrate 30, a silicon nitride (Si.sub.3 N.sub.4) insulating layer 32, an amorphous silicon layer 34 (aSi), an aluminium source S and a drain D. The lower capacitor plate is formed from an indium - tin oxide layer 38. The connection between the TFT and the plate is by a drain D extended by a tab 40 following a contact hole 42 made in insulating layer 32. The complete circuit is constituted by a plurality of such structures arranged in matrix form. The grids G are constituted by connection rows 44 and the sources by columns 46.
The process for producing such a structure involves five masking levels:
Such a process suffers from two disadvantages. Firstly a number of masking operations are required. It then necessitates the etching of the sources and the drains being selective and non-polluting with respect to the amorphous silicon, which must be protected by an adequate passivation, which must not produce an accumulation zone on the upper interface.
Another procedure for producing TFT's is known, in which unlike in the first-mentioned process, the TFT has its source and drain contacts in the lower part and its grid in the upper part. This procedure is described by M. MATSUMURA et al. in the article entitled "Amorphous silicon integrated circuit, published in "Proceedings of the IEE", vol. 68, No. 10, October 1980, pp. 1349-1350 and is illustrated by FIG. 3. On to a glass support 50 is deposited an amorphous silicon layer 52, followed by a n.sup.+ doped silicon layer, which is then etched to form the source contact 54 and drain contact 56. An insulating silica layer 58 is deposited on the entity. Openings 60, 62 are formed
REFERENCES:
patent: 4024626 (1977-05-01), Leupp et al.
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patent: 4188095 (1980-02-01), Nishimura et al.
patent: 4332075 (1982-06-01), Ota et al.
patent: 4366614 (1983-01-01), Kumurdjian
Gallagher, Electronics International, vol. 55, No. 10, May 1982, N.Y., pp. 94, 96.
Coissard Pierre
Morin Francois
Richard Joseph
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