Multiple-level memory with analog read

Details Multiple-level memory with analog read Multiple-level memory with analog read

2008-01-31

2010-06-29

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Floating gate

Multiple values

C365S185240

Reexamination Certificate

active

07746692

ABSTRACT:
A memory circuit includes a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein, and a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells. The circuit further includes multiple sense amplifiers, each of the sense amplifiers being connected to a corresponding one of the column lines and being operative to detect an electric charge stored in a selected one of the memory cells coupled to the corresponding column line and to generate an analog signal indicative of the stored electric charge. An analog multiplexer is connected to the sense amplifiers. The analog multiplexer is operative to receive the respective analog signals from the sense amplifiers and to generate an analog output signal having a magnitude which varies in time as a function of the respective analog signals from the sense amplifiers.

REFERENCES:
patent: 5896332 (1999-04-01), Brauch
patent: 2004/0085794 (2004-05-01), Perner
patent: 2006/0083097 (2006-04-01), Frulio et al.

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