Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-02-01
2010-11-02
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C377S064000
Reexamination Certificate
active
07825888
ABSTRACT:
A shift register circuit comprises a first transistor between a gate line output terminal and a clock terminal, a second transistor between the gate line output terminal and a first power supply terminal, a third transistor between a carry signal output terminal and the clock terminal and a fourth transistor between the carry signal output terminal and the first power supply terminal. Gates of the second and fourth transistors are connected to each other. A fifth transistor connected between a gate of the first transistor and a second power supply terminal and a sixth transistor connected between a gate of the third transistor and the second power supply terminal have gates both of which are connected to an input terminal. With this constitution, it is possible to suppress an influence between two synchronous output signals outputted from the shift register circuit.
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Murai Hiroyuki
Tobita Youichi
Hjerpe Richard
Mitsubishi Electric Corporation
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Sheng Tom V
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