Static MOS memory cell using inverted N-channel field-effect tra

Details Static MOS memory cell using inverted N-channel field-effect tra Static MOS memory cell using inverted N-channel field-effect tra

1979-02-12

1982-10-05

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 41, 357 59, 365182, 365222, 357 23, G11C 1140, H01L 2904, H01L 2978

Patent

active

043529976

ABSTRACT:
A storage cell employs two conventional N-channel MOS transistors and an inverted N-channel field-effect transistor along with an implanted polysilicon resistor and a resistor implanted under field oxide which functions as a junction field effect transistor. All of the transistors and a storage node as well as a voltage supply line are in one continuous moat region for a dense layout with a minimum of contacts. One MOS transistor is the access device connected between a bit line and the storage node with its gate connected to an address line. The other MOS transistor connects the storage node to the supply line and has its gate controlled by a second node which is connected to the supply line by a polycrystalline silicon strip which is the source-to-drain path of the inverted field-effect transistor; the gate of this device is a part of the moat which forms the storage node.

REFERENCES:
patent: 3576571 (1971-04-01), Booher
patent: 3618053 (1971-11-01), Hudson et al.
patent: 3699544 (1972-10-01), Joynson et al.
patent: 3876993 (1975-04-01), Cavanaugh
patent: 3922650 (1975-11-01), Schaffer
patent: 3955181 (1976-05-01), Raymond, Jr.
patent: 4031608 (1977-06-01), Togei et al.
patent: 4070653 (1978-01-01), Rao et al.
patent: 4139786 (1979-02-01), Raymond, Jr. et al.
Helwig, "Dynamic 4-FET Storage Cell"; IBM Tech. Discl. Bull.; vol. 15, No. 7, pp. 2205-2206; 12/72.

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