Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2008-07-16
2010-06-01
Li, Aimee J (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reexamination Certificate
active
07730283
ABSTRACT:
Embodiments of the invention provide a processor for executing instructions. In one embodiment, the processor includes circuitry to receive a load instruction and a store instruction to be executed in the processor and detect a conflict between the load instruction and the store instruction. Detecting the conflict includes determining if load-store conflict information indicates that the load instruction previously conflicted with the store instruction. The load-store conflict information is stored for both the load instruction and the store instruction. The processor further includes circuitry to schedule execution of the load instruction and the store instruction so that execution of the load instruction and the store instruction do not result in a conflict.
REFERENCES:
patent: 5625789 (1997-04-01), Hesson et al.
patent: 5751946 (1998-05-01), Afsar et al.
patent: 5809275 (1998-09-01), Lesartre
patent: 5884061 (1999-03-01), Hesson et al.
patent: 5903749 (1999-05-01), Kenner et al.
patent: 6021485 (2000-02-01), Feiste et al.
patent: 6141747 (2000-10-01), Witt
patent: 6308242 (2001-10-01), Kim
patent: 6308260 (2001-10-01), Le et al.
patent: 6349382 (2002-02-01), Feiste et al.
patent: 6463514 (2002-10-01), Ray et al.
patent: 6481251 (2002-11-01), Meier et al.
patent: 6598156 (2003-07-01), Aora
patent: 6728867 (2004-04-01), Kling
patent: 7058751 (2006-06-01), Kawarai et al.
patent: 7103880 (2006-09-01), Morris et al.
patent: 7461238 (2008-12-01), Luick
patent: 2005/0149703 (2005-07-01), Hammond et al.
patent: 2007/0288725 (2007-12-01), Luick
patent: 2007/0288726 (2007-12-01), Luick
patent: 0436092 (1991-07-01), None
patent: 0871109 (1998-10-01), None
patent: 0250668 (2002-06-01), None
Free On-Line Dictionary of Computing. www.foldoc.org search term: cache © 1997.
Hirata et al., An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads, Proceedings of the 19th Annual International Symposium on Computer Architecture, 1992, pp. 136-145.
Weiss et al., Instruction Issue Logic in Pipelined Supercomputers, IEEE Transactions on Computers, vol. C-33, Issue 11, Nov. 1984, pp. 110-118.
Austin et al., Dynamic Dependency Analysis of Ordinary Programs, Proceedings of the 19th Annual International Symposium on Computer Architecture, May 19-21, 1992, pp. 342-351.
Shen et al., Modern Processor Design—Fundamentals of Superscalar Processors, Beta Edition, McGraw Hill, USA, 2003, pp. 196-201.
Mikko Herman Lipasti, Value Locality and Speculative Execution, Dissertation for Carnegie Mellon University, Apr. 1997.
Office Action dated Jan. 9, 2008 for U.S. Appl. No. 11/422,647.
International Business Machines - Corporation
Li Aimee J
Patterson & Sheridan LLP
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