Semiconductor memory

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185180, C365S072000, C257S314000, C257S315000

Reexamination Certificate

active

07742337

ABSTRACT:
A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

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Japanese Office Action dated Dec. 15, 2009 from corresponding Japanese Patent Application No. 2004-113752 and its English translation.

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