Integrated circuit micro-module

Details Integrated circuit micro-module Integrated circuit micro-module

2009-06-05

2010-11-30

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S015000, C438S025000, C438S051000, C438S107000, C438S108000, C257SE21499, C257SE21536, C257SE21538, C257SE21705

Reexamination Certificate

active

07842544

ABSTRACT:
Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate. Molding material is applied over the top surface of the substrate and the microsystems to form a molded structure. Portions of the substrate can be removed. The molded structure can be singulated to form individual integrated circuit packages. Each of the integrated circuit packages contains at least one microsystem. Various embodiments involve forming conductive pads on the top surface of the substrate instead of the metal vias.

REFERENCES:
patent: 6734569 (2004-05-01), Appelt et al.
patent: 6911355 (2005-06-01), Farnworth et al.
patent: 7232733 (2007-06-01), Lotfi et al.
patent: 7473579 (2009-01-01), Sharifi et al.
patent: 2003/0206680 (2003-11-01), Bakir et al.
patent: 2007/0111385 (2007-05-01), Magerlein et al.
patent: 2007/0132086 (2007-06-01), Agraharam et al.
patent: 2007/0181979 (2007-08-01), Beer et al.
patent: 2008/0116564 (2008-05-01), Yang et al.
patent: 2008/0157336 (2008-07-01), Yang
patent: 2008/0174020 (2008-07-01), Ga
patent: 2008/0201944 (2008-08-01), Sakamoto et al.
patent: 2009/0159875 (2009-06-01), Chabinyc et al.
patent: 2010/0127375 (2010-05-01), Galera et al.
Adler, Micheal. “GE High Density Interconnect: A Solution to the System Interconnect Problem.” Downloaded on Jul. 20, 2009 from IEEE Xplore.
Office Action dated Aug. 23, 2010 from U.S. Appl. No. 12/479,707.
Tuominen, Risto. “IMB Technology for Embedding Active Components into a Substrate.” SEMICON Europa, Munich, Germany. Apr. 4, 2006.
Keser et al. “Advanced Packaging: The Redistributed Chip Package.” IEEE Transactions on Advanced Packaging, vol. 31, No. 1, Feb. 2008.
Knickerbocker et al. “3-D Silicon Integration Silicon Packaging Technology Using Silicon Through-Vias.” IEEE Journal of Solid State Circuits, vol. 41, No. 8, Aug. 2006.
Sharifi et al. “Self-Aligned Wafer-Level Integration Technology with High-Density Interconnects Embedded Passives.” IEEE Transactions on Advanced Packaging, vol. 30, No. 1, Feb. 2007.
JMD's Multi-Layer Organic (MLO) technology, downloaded Nov. 2007 from www.jacketmicro.com/technology/.
Yang et al. “3D Multilayer Integration and Packaging or Organic/Paper Low-cost Substrates for RF and Wireless Applications.” IEEE 2007.
Pieters et al. “3D Wafer Level Packaging Approach Towards Cost Effective Low Loss High Density 3D Stacking.” 7thInternational Conference on Electronics Packaging Technology, 2006.
Tummala et al. “Microsystems Packaging from Milli to Microscale to Nanoscale.” IEEE 2004.
Tummala, Rao R. “Packaging: Past, Present and Future.” 6thInternational Conference on Electronic Packaging Technology, 2005.
Lim, Sung Kyu. “Physical Design for 3D Systems on Package.” IEEE Design & Test of Computers, 2005.
Yoon et al. “Polymer Embedded Module for SiP Application.” 2004 Electronics Packaging Technology Conference.
Tummala, Rao R. “SOP: What Is It and Why? A New Microsystem-Integration Technology Paradigm—Moore's Law for System Integration of Miniaturized Convergent Systems of the Next Decade.” IEEE Transactions on Advanced Packaging, vol. 27, No. 2, May 2004.
Souriau et al. “Wafer Level Processing of 3D System in Package for RF and Data Applications.” 2005 Electronic Components and Technology Conference.
International Search Report dated Aug. 25, 2010 from International Patent Application No. PCT/US2010/020555.
Written Opinion dated Aug. 25, 2010 from International Patent Application No. PCT/US2010/020555.
Notice of Allowance dated Sep. 20, 2010 from U.S. Appl. No. 12/390,349.

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