Integrated dual layer passivation process to suppress stress-ind

Details Integrated dual layer passivation process to suppress stress-ind Integrated dual layer passivation process to suppress stress-ind

1995-04-04

1996-12-10

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437241, H01L 21316, H01L 21318

Patent

active

055830773

ABSTRACT:
Integrated circuits may be passivated by means of two deposited layers--one of phosphosilicate glass and one of silicon nitride. It was observed that if significant time elapsed between the deposition of the phosphosilicate and the silicon nitride, appreciable degradation of the underlying metallurgy, in the form of voids, occurred. This was traced to a change, over time, in the stresses to which the metallurgy was being subjected--from tensile to compressive. This problem has been solved in the present invention by the provision of a dry environment in which to store the integrated circuits between the application of the two passivation layers.

REFERENCES:
patent: 4455325 (1984-06-01), Razouk
patent: 5139971 (1992-08-01), Giridhar et al.
patent: 5336640 (1994-08-01), Sato
Wolf, Stanley, "Silicon Processing For The VLSI Era", vol. 1, (1986) pp. 188-189, 332-333, 516-517.

Affiliated with

Also associated with

Rating

Integrated dual layer passivation process to suppress stress-ind does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated dual layer passivation process to suppress stress-ind, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated dual layer passivation process to suppress stress-ind will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-423996