Static information storage and retrieval – Floating gate
Reexamination Certificate
2008-10-27
2010-10-26
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Floating gate
C365S185240, C365S185220, C365S185110, C365S189180, C365S189190
Reexamination Certificate
active
07821824
ABSTRACT:
A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information.
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Ishikawa Eiichi
Kataoka Takeshi
Shinagawa Yutaka
Suzukawa Kazufumi
Tanaka Toshihiro
Hidalgo Fernando N
Ho Hoai V
Miles & Stockbridge P.C.
Renesas Electronics Corporation
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