Apparatus, system, and method for discontiguous multiple...

Details Apparatus, system, and method for discontiguous multiple... Apparatus, system, and method for discontiguous multiple...

2008-01-03

2010-10-26

Pan, Daniel (Department: 2183)

Electrical computers and digital processing systems: processing

Architecture based instruction processing

Multiprocessor instruction

C712S216000

Reexamination Certificate

active

07822948

ABSTRACT:
An apparatus, system, and method are disclosed for discontiguous multiple issue of instructions. An assignment unit assigns a plurality of instruction blocks to a plurality of issue units. The plurality of issue units each comprises a renaming map that maps each architecturally visible register address to a rename register. Each issue unit maps each architecturally visible register in the decoded instruction to a register placeholder if the renaming map entry for that architecturally visible register is invalid else maps the architecturally visible register in the decoded instruction to a rename register if the rename register entry is valid. Each issue unit further receives predecessor mapping information from the renaming map of the issue unit's predecessor issue unit in response to the assignment unit identifying a relationship with the predecessor issue unit and the final mapping information being available from the predecessor issue unit.

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