Delay locked loop in semiconductor memory device

Details Delay locked loop in semiconductor memory device Delay locked loop in semiconductor memory device

2008-05-01

2010-06-08

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000

Reexamination Certificate

active

07733140

ABSTRACT:
A delayed lock loop for preventing a stuck fail in a dead-zone includes a clock buffering block for generating a first and a second internal clock signals; a phase comparison block for delaying a feedback signal by a first predetermined value and for respectively comparing a phase of a delayed feedback signal and a phase of the feedback signal with a phase of the external clock signal; a clock selecting block for selecting one of the first and second internal clock signals based on one comparison result to thereby generate a selected internal clock signal; a stuck checking block for determining a delay value based on the other comparison result; a delay line block for delaying the selected internal clock signal by the delay value; and an output buffer for buffering an outputted signal from the delay line block to thereby generating a DLL clock signal.

REFERENCES:
patent: 5977801 (1999-11-01), Boerstler
patent: 6137328 (2000-10-01), Sung
patent: 6366148 (2002-04-01), Kim
patent: 6518807 (2003-02-01), Cho
patent: 2002/0084857 (2002-07-01), Kim
patent: 2003/0117194 (2003-06-01), Lee
patent: 2003/0174003 (2003-09-01), Nogami

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