Comparator and A/D converter

Details Comparator and A/D converter Comparator and A/D converter

2006-04-18

2010-10-26

Nguyen, Hai L (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S055000, C327S065000

Reexamination Certificate

active

07821303

ABSTRACT:
A comparator used in a parallel-type A/D converter, wherein a comparator100includes reset transistors mra and mrb. When the comparator100is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator100is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.

REFERENCES:
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Sushihara, K., et al., “7b 450MSample/s 50mW CMOS ADC in 0.3mm2”, ISSCC 2002 / SESSION 10 / High-Speed ADCs, ISSCC 2002 Visuals Supplement, 2002, vol. 10.3, IEEE.

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