Non-volatile semiconductor memory device and method of...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185030

Reexamination Certificate

active

07835182

ABSTRACT:
The device has a data write mode to boost a first boost channel region that contains a non-write selected memory cell and non-selected memory cells located closer to the first selection gate transistor, and a second boost channel region that contains non-selected memory cells located closer to the second selection gate transistor than the selected memory cell, both electrically separated from each other. In this mode, a write non-selection voltage applied to a non-selected memory cell next to the second selection gate transistor is switched, at least in two stages, between a lower voltage V1than a write non-selection voltage Vm applied to other non-selected memory cells in the NAND cell unit and a higher voltage V2than the lower voltage (V1<V2≦Vm).

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Jae-Duk Lee, et al., “A new Programming Disturbance Phenomenon in NAND Flash Memory by Source/Drain Hot-Electrons Generated by GIDL Current”, IEEE, NVSMW 2006, 21stNon-Volatile Semiconductor Memory Workshop, Feb. 12-16, 2006, 5 Pages.
Ki-Tae Park, et al., “Scalable Wordline Shielding Scheme using Dummy Cell beyond 40nm NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell”, Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, C-6-4L, 2006, pp. 298-299.

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