Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-08-08

2010-02-16

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185250

Reexamination Certificate

active

07663929

ABSTRACT:
A memory cell array forms a plurality of control areas in a direction orthogonal to the direction of extension of a bit line. A sense amplifier initially charges a bit line in each control area in the memory cell array with a charging voltage controlled by a respective individual bit-line control signal. Bit-line control signal generator circuits are provided plural in accordance with the control areas in the memory cell array. Each bit-line control signal generator circuit receives the potential on a cell source line in a corresponding control area, individually generates and provides the bit-line control signal in the each control area in accordance with the received voltage on the cell source line in each control area.

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