Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Reexamination Certificate
2007-04-30
2010-12-14
Smith, Matthew S (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
C257S401000, C257SE29040, C257SE29120
Reexamination Certificate
active
07851889
ABSTRACT:
Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well. An area (510) comprising regions of alternating conductivities is then formed in the semiconductor well.
REFERENCES:
patent: 6066878 (2000-05-01), Neilson
patent: 6121089 (2000-09-01), Zeng et al.
patent: 6777746 (2004-08-01), Kitagawa et al.
patent: 6900109 (2005-05-01), Onishi et al.
patent: 6960807 (2005-11-01), Pendharkar
patent: 7301220 (2007-11-01), Udrea
patent: 2002/0132406 (2002-09-01), Disney
patent: 2003/0227052 (2003-12-01), Ono et al.
patent: 2005/0012114 (2005-01-01), Tada et al.
patent: 2005/0167742 (2005-08-01), Challa et al.
patent: 2008/0296669 (2008-12-01), Pendharkar et al.
Hower, P., et al., A rugged LDMOS for LBC5 Technology, Proceedings on the 17th International Symposium on Power Semiconductor Devices & IC's, May 23-26, 2005.
Williams, R., et al., The Influence of N+ Source Region on Parasitic PNP Conduction In Integrated N- Channel DMOS, Proceedings of the 6th International Symposium on Volume , Issue , May 31-Jun. 3, 1994 pp. 143-148.
International Search Report for coordinating PCT Application No. PCT/US2008/060397 mailed Sep. 24, 2008.
Bose Amitava
Khemka Vishnu K.
Roggenbauer Todd C.
Zhu Ronghua
Freescale Semiconductor Inc.
Ingrassia Fisher & Lorenz P.C.
Jefferson Quovaunda
Smith Matthew S
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