Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-12-12
2010-06-08
Le, Thong Q (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170, C365S185240, C365S185290, C365S185150
Reexamination Certificate
active
07733702
ABSTRACT:
A semiconductor memory device includes a memory cell array of NAND cell units. The NAND cell unit includes a plurality of electrically erasable programmable nonvolatile memory cells connected serially, and a first and a second selection transistor provided to connect both ends of the memory cells to a bit line and a source line, respectively. The semiconductor memory device also includes dummy cells inserted in the NAND cell unit adjacent to the first and second selection transistors, respectively. The dummy cells in the NAND cell unit are erased simultaneously with the memory cells under a weaker erase potential condition than that for the memory cells and set in a higher threshold distribution than an erased state of the memory cells.
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patent: 6134140 (2000-10-01), Tanaka et al.
patent: 7518920 (2009-04-01), Kang
patent: 2006/0039230 (2006-02-01), Kurata et al.
patent: 2006/0139997 (2006-06-01), Park et al.
patent: 2006-186359 (2006-07-01), None
Kabushiki Kaisha Toshiba
Le Thong Q
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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