Trimmable delay locked loop circuitry with improved...

Details Trimmable delay locked loop circuitry with improved... Trimmable delay locked loop circuitry with improved...

2008-10-08

2010-06-01

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000, C365S233100

Reexamination Certificate

active

07728639

ABSTRACT:
Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.

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patent: 2008/0136475 (2008-06-01), Gomm et al.

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