Frequency and phase detection circuit in NRZ bit synchronous sys

Details Frequency and phase detection circuit in NRZ bit synchronous sys Frequency and phase detection circuit in NRZ bit synchronous sys

1989-12-21

1992-05-26

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307527, 307471, 307479, 328133, 375120, H03K 526, H03K 906

Patent

active

051171350

ABSTRACT:
A frequency and phase detection circuit in an NRZ bit synchronous system by simultaneously retiming an NRZ input with an in-phase clock and an inverse-phase clock, respectively. A first frequency and phase difference is extracted by supplying the retimed NRZ with the in-phase clock and the delay-compensated NRZ input to an exclusive OR-gate. A second frequency and phase difference is extracted by supplying the retimed NRZ with the inverse-phase clock and the retimed NRZ with the in-phase clock to another exclusive OR-gate.

REFERENCES:
patent: 4400667 (1983-08-01), Belkin
patent: 4422176 (1983-12-01), Summers
patent: 4527277 (1985-07-01), Kosaka et al.
patent: 4535459 (1985-08-01), Hogge, Jr.
patent: 4571738 (1986-02-01), Vance
patent: 4683437 (1987-07-01), Javeri
patent: 4942370 (1990-07-01), Shigemori

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