Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2008-02-12
2010-12-21
Nguyen, Dang T (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C365S185280
Reexamination Certificate
active
07855912
ABSTRACT:
A control apparatus programs, reads, and erases trapped charges representing multiple data bits from a charge trapping region of a NMOS dual-sided charge-trapping nonvolatile memory cell includes a programming circuit, an erasing circuit, and a reading circuit. The programming circuit provides a negative medium large program voltage to cell's gate along with positive drain and source voltage to inject hot carriers of holes to two charge trapping regions, one of a plurality of threshold adjustment voltages representing a portion of the multiple data bits to the drain and source regions to set the hot carrier charge levels to the two charge trapping regions. The erasing circuit provides a very large positive erase voltage to tunnel the electrons from cell's channel to whole trapping layer including the two charge trapping regions. The reading circuit generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages representative of multiple data bits, generates a drain voltage level to activate the charge-trapping nonvolatile memory cell.
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Hsu Fu-Chang
Lee Peter
Ackerman Stephen B.
Aplus Flash Technology Inc.
Knowles Billy
Nguyen Dang T
Saile Ackerman LLC
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