Semiconductor device and method of producing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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C257S510000, C257S513000, C257SE21546

Reexamination Certificate

active

07825489

ABSTRACT:
In a semiconductor device having element isolation made of a trench-type isolating oxide film13, large and small dummy patterns11of two types, being an active region of a dummy, are located in an isolating region10, the large dummy patterns11bare arranged at a position apart from actual patterns9, and the small dummy patterns11aare regularly arranged in a gap at around a periphery of the actual patterns9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film13ais improved, and surface flatness of the semiconductor device becomes preferable.

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United States Notice of Allowance issued in U.S. Appl. No. 12/265,430, mailed Jan. 29, 2010.
Japanese Office Action, with English translation, issued in Japanese Patent Application No. 11-355645, mailed Jul. 27, 2010.

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