Circuit arrangement for producing a defined output signal

Details Circuit arrangement for producing a defined output signal Circuit arrangement for producing a defined output signal

2006-08-11

2010-10-26

Donovan, Lincoln (Department: 2816)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

C327S088000, C340S652000, C324S537000, C324S555000

Reexamination Certificate

active

07821754

ABSTRACT:
A circuit arrangement for producing a defined output signal in CMOS integrated circuit is provided in which the output of a sensor signal conditioning circuit is connected to the drain terminal of a first N channel depletion transistor, to a source terminal of a second N channel depletion transistor and to the output (OUT) of an integrated CMOS circuit. The gate terminals of the first and second N channel depletion transistors are connected to the output (VP) of a control circuit and the first terminal of a discharge resistance. The second terminal of the discharge resistance and the source terminal of the first N channel depletion transistor are connected to a potential VSS, and the drain terminal of the second N channel depletion transistor is connected to a potential VDD.

REFERENCES:
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patent: 2002/0089382 (2002-07-01), Yang
patent: 4400437 (1994-07-01), None
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The International Search Report for PCT/DE2006/001412, filed Jan. 30, 2007.

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