Single-crystal – oriented-crystal – and epitaxy growth processes; – Forming from vapor or gaseous state
Reexamination Certificate
2006-05-30
2010-10-12
Kunemund, Robert M (Department: 1714)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Forming from vapor or gaseous state
C117S089000, C117S093000, C117S098000, C117S101000
Reexamination Certificate
active
07811382
ABSTRACT:
A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer. A low temperature silicon layer is then epitaxially grown with tensile strain, correlated to the tensile strain of the thin silicon layer, on the thin silicon layer using trisilane at a temperature preferably not in excess of 500 degrees Celsius. The resulting tensile strain, correlated to the strain of the thin silicon layer, is thus also correlated to the germanium concentration of the relaxed SiGe layer. The thickness of the low temperature silicon layer, using the trisilane at low temperature, is significantly greater than what would normally be expected for a silicon layer of that tensile strain.
REFERENCES:
patent: 6831292 (2004-12-01), Currie et al.
patent: 6881632 (2005-04-01), Fitzgerald et al.
patent: 7202142 (2007-04-01), Lee et al.
patent: 2004/0140479 (2004-07-01), Akatsu
Lauer, Isaac et al.; “Fully Depleted n-MOSFETs on Supercritical Thickness Strained SOI”; IEEE Electron Device Letters; Feb. 2004; pp. 83-85; vol. 25, No. 2; IEEE.
Thean, A.V.Y. et al; “Performance of Super-Critical Strained-Si Directly On Insulator (SC-SSOI) CMOS Based on 90-nm Process Technology”; VLSI Technology Symposium; Jun. 2005.
Barr Alexander L.
Nguyen Bich-Yen
Sadaka Mariam G.
Thean Voon-Yew
White Ted R.
Chiu Joanna G.
Clingan, Jr. James L.
Freescale Semiconductor Inc.
Kunemund Robert M
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