Delay circuit of delay locked loop having single and dual...

Details Delay circuit of delay locked loop having single and dual... Delay circuit of delay locked loop having single and dual...

2008-07-14

2010-06-08

Luu, An T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S158000, C327S270000, C327S271000

Reexamination Certificate

active

07733147

ABSTRACT:
A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.

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patent: 6836166 (2004-12-01), Lin et al.
patent: 7016452 (2006-03-01), Partsch et al.
patent: 7161397 (2007-01-01), Lee et al.
patent: 7184509 (2007-02-01), Cho et al.
patent: 7236028 (2007-06-01), Choi
patent: 7282974 (2007-10-01), Lee
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patent: 7336111 (2008-02-01), Lin et al.
patent: 1020030078129 (2003-10-01), None
patent: 1020060082498 (2006-07-01), None
patent: 1020070109683 (2007-11-01), None

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