Hybrid arithmetic logic unit

Details Hybrid arithmetic logic unit Hybrid arithmetic logic unit

2006-08-18

2010-11-02

Mai, Tan V (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S714000

Reexamination Certificate

active

07827226

ABSTRACT:
Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: a first stage that produces separate sum and carry results in a first cycle, and a second stage that produces a final result in one or more immediately subsequent cycles. While this produces final results in two or more clock cycles, useable partial results are produced each cycle, thus maintaining a one operation per clock cycle throughput.

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