Method for erasing/programming/correcting a multi-level cell...

Details Method for erasing/programming/correcting a multi-level cell... Method for erasing/programming/correcting a multi-level cell...

2007-11-19

2010-10-26

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185270, C365S185180, C365S185030

Reexamination Certificate

active

07821838

ABSTRACT:
A memory operating method includes the following steps. First, a memory including a charge storage structure is provided. Next, first type charges are injected into the charge storage structure such that a threshold level of the memory is higher than an erase level. Then, second type charges are injected into the charge storage structure such that the threshold level of the memory is lower than a predetermined bit level. Next, first type charges are injected into the charge storage structure such that the threshold level of the memory approximates to or is equal to the predetermined bit level.

REFERENCES:
patent: 6801456 (2004-10-01), Hsu et al.

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