Mitigation of data corruption from back pattern and program...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185130, C365S185140, C365S185170

Reexamination Certificate

active

07830718

ABSTRACT:
In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.

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patent: 2008/0310224 (2008-12-01), Roohparvar et al.
patent: 2009/0129146 (2009-05-01), Sarin et al.
U.S. Appl. No. 11/818,863, filed Jun. 15, 2007, Roohparvar et al.

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