Decoder with memory

Details Decoder with memory Decoder with memory

2008-04-23

2010-06-15

Tan, Vibol (Department: 2819)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C326S108000, C326S093000

Reexamination Certificate

active

07738314

ABSTRACT:
In one embodiment, a decoder for decoding an address having a plurality of bits ranging from a first address bit a1to a last address bit aN, each address bit being either true or false is provided that includes: a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true; a (n+1)th switch coupling the dynamic OR node to ground, the (n+1)th switch being controlled such that it turns on if the dynamic OR node is charged, whereby the pre-charged dynamic OR node discharges if the dynamic OR node remains charged; an odd plurality of inverters coupled in series with the dynamic OR node; and a word line driven by the odd plurality of inverters.

REFERENCES:
patent: 5291076 (1994-03-01), Bridges et al.
patent: 5737270 (1998-04-01), Oppold et al.
patent: 6172531 (2001-01-01), Aipperspach et al.

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