Integrated decision feedback equalizer and clock and data...

Details Integrated decision feedback equalizer and clock and data... Integrated decision feedback equalizer and clock and data...

2004-04-13

2010-10-26

Payne, David C (Department: 2611)

Pulse or digital communications

Equalizers

Automatic

C375S232000, C375S237000, C375S376000, C327S057000, C327S202000, C327S166000, C327S176000

Reexamination Certificate

active

07822113

ABSTRACT:
In an integrated decision feedback equalizer and clock and data recovery circuit one or more flip-flops and/or latches may be shared. One or more flip-flops and/or latches may be used in retiming operations in a decision feedback equalizer and in phase detection operations in a clock recovery circuit. Outputs of the flip-flops and/or latches may be used to generate feedback signals for the decision feedback equalizer. The output of a flip-flop and/or latches may be used to generate signals that drive a charge pump in the clock recovery circuit.

REFERENCES:
patent: 4649438 (1987-03-01), Shimizu et al.
patent: 4787097 (1988-11-01), Rizzo
patent: 4862484 (1989-08-01), Roberts et al.
patent: 5179302 (1993-01-01), Wagner
patent: 5581585 (1996-12-01), Takatori et al.
patent: 5671252 (1997-09-01), Kovacs
patent: 5684434 (1997-11-01), Mann et al.
patent: 5774505 (1998-06-01), Baugh
patent: 5786951 (1998-07-01), Welland
patent: 5940441 (1999-08-01), Cranford
patent: 6064272 (2000-05-01), Rhee
patent: 6069522 (2000-05-01), Venkatraman
patent: 6144697 (2000-11-01), Gelfand
patent: 6233107 (2001-05-01), Minuhin
patent: 6285709 (2001-09-01), Alelyunas
patent: 6340899 (2002-01-01), Green
patent: 6366146 (2002-04-01), Fredriksson
patent: 6542038 (2003-04-01), Nishimura
patent: 6556637 (2003-04-01), Moriuchi
patent: 6670853 (2003-12-01), Kim
patent: 6807225 (2004-10-01), Tonietto
patent: 6873669 (2005-03-01), Nakamura
patent: 6919759 (2005-07-01), Chuan
patent: 6931088 (2005-08-01), Tomita
patent: 6968167 (2005-11-01), Wu et al.
patent: 6968168 (2005-11-01), Collier
patent: 7016406 (2006-03-01), Phanse
patent: 7054606 (2006-05-01), Sheng
patent: 7085328 (2006-08-01), Lin
patent: 7092474 (2006-08-01), Cao
patent: 7272178 (2007-09-01), Rahman
patent: 7302461 (2007-11-01), Mukherjee
patent: 7321621 (2008-01-01), Popescu
patent: 7330508 (2008-02-01), Momtaz
patent: 7353245 (2008-04-01), Healey
patent: 7436882 (2008-10-01), Momtaz
patent: 7471904 (2008-12-01), Kaneda
patent: 7522847 (2009-04-01), Momtaz
patent: 2001/0033407 (2001-10-01), Cao
patent: 2003/0165208 (2003-09-01), Carter et al.
patent: 2004/0151268 (2004-08-01), Hidaka
patent: 2005/0019042 (2005-01-01), Kaneda
patent: 0808046 (1997-11-01), None
patent: 1 331 779 (2003-07-01), None
patent: 0213423 (2002-04-01), None
patent: 2004002023 (2003-12-01), None
Lee, T. H. et al. “A 155-MHz Clock Recovery Delay- and Phase-Locked Loop.” IEEE Journal of Solid-State Circuits, IEEE, Inc., New York, US., vol. 27, No. 12, Dec. 1, 1992, pp. 1736-1746.
European Search Report for Application No. EP04028869 ; date of completion Nov. 10, 2005, The Hague (2 pages). Annex to the European Search Report on European Patent Application No. EP04028869 (1 page).
Thomas E. Lee, et al., “A 155-MHz Clock Recovery Delay- and Phase-Locked Loop,”IEEE Journal of Solid-State Circuits, Dec. 1992, pp. 1736-1746, vol. SC-27.
Wikipedia, Latch (electronics), http://en.wikipedia.org/wiki/Gated—D—latch, Feb. 9, 2010.
Wikipedia, Flip-flop (electronics), http://en.wikipedia.org/wiki/Flip-flop—(electronics), Feb. 9, 2010.
Request for Certificate of Correction regarding U.S. Appl. No. 10/774,724 mailed on Apr. 28, 2009.
Notice of Allowance and Fees Due (PTOL-85) regarding U.S. Appl. No. 10/774,724 mailed on Dec. 22, 2008.
Amendment After Final or under 37CFR 1.312 regarding U.S. Appl. No. 10/774,724 mailed on Dec. 22, 2008.
Advisory Action (PTOL-303) regarding U.S. Appl. No. 10/774,724 mailed on Dec. 9, 2008.
Amendment After Final regarding U.S. Appl. No. 10/774,724 mailed on Dec. 8, 2008.
Amendment After Final regarding U.S. Appl. No. 10/774,724 mailed on Oct. 30, 2008.
Final Rejection regarding U.S. Appl. No. 10/774,724 mailed on Jul. 30, 2008.
Amendment/Req. Reconsideration-After Non-Final Reject regarding U.S. Appl. No. 10/774,724 mailed on Jun. 5, 2008.
Non-Final Rejection regarding U.S. Appl. No. 10/774,724 mailed on Feb. 5, 2008.
Amendment Submitted/Entered with Filing of CPA/RCE regarding U.S. Appl. No. 10/774,724 mailed on Jan. 11, 2008.
Pre-Brief Appeal Conference decision regarding U.S. Appl. No. 10/774,724 mailed on Dec. 12, 2007.
Pre-Brief Conference request regarding U.S. Appl. No. 10/774,724 mailed on Oct. 29, 2007.
Advisory Action (PTOL-303) regarding U.S. Appl. No. 10/774,724 mailed on Oct. 5, 2007.
Amendment Submitted/Entered with Filing of CPA/RCE regarding U.S. Appl. No. 10/774,724 mailed on Aug. 29, 2007.
Final Rejection regarding U.S. Appl. No. 10/774,724 mailed on May 29, 2007.
Amendment/Req. Reconsideration-After Non-Final Reject regarding U.S. Appl. No. 10/774,724 mailed on Mar. 2, 2007.
Non-Final Rejection regarding U.S. Appl. No. 10/774,724 mailed on Nov. 2, 2006.
Notice of Allowance and Fees Due (PTOL-85) regarding U.S. Appl. No. 10/774,725 mailed on Sep. 21, 2007.
Amendment/Req. Reconsideration-After Non-Final Reject regarding U.S. Appl. No. 10/774,725 mailed on Jul. 12, 2007.
Non-Final Rejection regarding U.S. Appl. No. 10/774,725 mailed on May 4, 2007.
Notice of Allowance and Fees Due (PTOL-85) regarding U.S. Appl. No. 10/774,965 mailed on Jun. 12, 2008.
Amendment After Final or under 37CFR 1.312 regarding U.S. Appl. No. 10/774,965 mailed on May 21, 2008.
Final Rejection regarding U.S. Appl. No. 10/774,965 mailed on Apr. 4, 2008.
Amendment/Req. Reconsideration-After Non-Final Reject regarding U.S. Appl. No. 10/774,965 mailed on Jan. 16, 2008.
Non-Final Rejection regarding U.S. Appl. No. 10/774,965 mailed on Sep. 20, 2007.
Amendment/Req. Reconsideration-After Non-Final Reject regarding U.S. Appl. No. 10/774,965 mailed on Jul. 27, 2007.
Non-Final Rejection regarding U.S. Appl. No. 10/774,965 mailed on May 9, 2007.
Garrido et ai, “A comparative study of two adaptive continuous-time filters for decision feedback equalization read channels” Jun. 9-12, 1997, Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on, pp. 89-92 vol. 1 in “List of references cited by examiner” regarding U.S. Appl. No. 10/774,724 mailed on Jul. 30, 2008.
European Search Report and Annex for Application No. EP04026608; date of completion Dec. 8, 2005, The Hague (2 pages). Cited in Information Disclosure Statement (IDS) Filed (SB/08) regarding U.S. Appl. No. 10/774,725 mailed on Feb. 3, 2006.
European Search Report and Annex for Application No. EP04026612; date of completion Dec. 8, 2005, The Hague (2 pages). Cited in Information Disclosure Statement (IDS) Filed (SB/08) regarding U.S. Appl. No. 10/774,965 mailed on Feb. 3, 2006.
Garrido et al, “A comparative study of two adaptive continuous-time filters for decision feedback equalization read channels” Jun. 9-12, 1997, Circuits and Systems, 1997, ISCAS '97., Proceedings of 1997 IEEE International Symposium on, pp. 89-92 vol. 1.
European Search Report and Annex for Application No. EP04026608; date of completion Dec. 8, 2005, The Hague (2 pages).
European Search Report and Annex for Application No. EP04026612; date of completion Dec. 8, 2005, The Hague (2 pages).

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